1. Field of the Invention
The present invention relates to a semiconductor device, such as a complementary metal oxide semiconductor (CMOS) transistor, having a P-well and an N-well on a Silicon-On-Insulator (hereinafter, referred to as SOI) substrate, and more particularly to a semiconductor device capable of removing the latch-up problem due to the complete isolation between the wells and a method for fabricating the same.
2. Description of the Prior Art
Generally, a high speed memory device is formed on an SOI substrate. The SOI substrate is made of a buried oxide layer formed on a silicon substrate and a single crystal silicon layer formed on the buried oxide layer. In an SOI substrate the parasitic capacitance of the devices is reduced due to the buried oxide layer, and therefore the device switching speed may increase.
However, the transistor formed on the SOI substrate has no bulk electrode (ground terminal) in the single crystal layer, so that the parasitic bipolar effect occurs, thereby causing a large leakage current between the adjacent PNP and NPN bipolar transistors. This is called the latch-up. Therefore, the break down voltage of the transistor is lowered and the characteristics of the transistor are degraded by the hot electrons. As a result, the reliability of device is deteriorated.
A conventional method to solve the above mentioned problem will be described with reference to FIG. 1. As shown in FIG. 1, a buried oxide layer 11 and a single crystal silicon layer 12 are formed on a predetermined region of a silicon substrate 10. Impurities are diffused into the single crystal silicon layer 12 to form wells. Thereafter, a field oxide layer 13 is formed on the single crystal silicon layer 12 by the thermal oxidation process and a field stop ion implantation layer 14 is formed beneath the field oxide layer 13 to prevent the leakage current from passing through the single crystal silicon layer 12. A gate oxide layer 15 and a polysilicon layer 16 for a gate are formed on each well and then impurities are implanted into the single crystal silicon layer 12 to form source/drain regions (not shown) . An oxide layer is formed on the resulting structure and etched without an etching mask so as to form spacers 17 on the sidewalls of the gate electrode.
Herein, the field oxide layer 13 is formed by the local oxidation of silicon (LOCOS) process leaving the single crystal silicon layer 12 to a thickness of 100 .ANG. to 1000 .ANG. between the field oxide layer 13 and the buried oxide layer 11. The remaining single crystal silicon layer 12 is doped so as to form the field stop ion implantation layer 14, which plays the role of a well electrode. That is to say, voltage is induced from the well to the region beneath the gate through the remaining silicon layer, and as a result, voltage at the region beneath the gate does not increase. However, the wells are not completely isolated by the field oxide layer formed according to the above mentioned conventional method, and therefore the latch-up problem is not effectively prevented.